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DS1225Y DATASHEET PDF

March 25, 2019

SEMICONDUCTOR. DSY. 64K Nonvolatile SRAM. PIN ASSIGNMENT. FEATURES. 10 years minimum data retention in the absence of external power. CC. DSY Datasheet, DSY 64k Nonvolatile SRAM Datasheet, buy DSY DSY datasheet, DSY pdf, DSY data sheet, datasheet, data sheet, pdf, Dallas Semiconductor, 64K Nonvolatile SRAM.

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DS1225Y-150IND

As VCC falls below approximately 3. The OE control signal should be kept inactive high during write cycles to avoid bus contention. If the Dztasheet high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in a high impedance state during this period.

Data is maintained in the absence of VCC without any additional support circuitry. EDIP is wave or hand soldered only.

Documents Flashcards Grammar checker. BB designates the week of manufacture. There is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing.

BB designates the week of manufacture. AA designates the year of manufacture. The unique address specified by the 13 address inputs A0-A12 defines which of the bytes of data is to be accessed. In a power down condition the voltage on any pin may not exceed the voltage on VCC. When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. The write cycle is terminated by the earlier rising edge of CE or WE.

All voltages are referenced to ground. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high-impedance state during this period. All voltages are referenced to ground.

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Valid data will be available to the eight data output drivers within tACC Access Time after the last address input signal is stable, providing that CE and OE access times are also satisfied. In a power down condition the voltage on any pin may not exceed the voltage on VCC. The later-occurring falling edge of CE or WE will determine the start of the write cycle. Data is maintained in the absence of VCC without any additional support circuitry.

The expected tDR is defined as starting at the date of manufacture. As VCC falls below approximately 3. Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode. The OE control signal should be kept inactive high during write cycles to avoid bus contention.

During power-up, when VCC rises above approximately 3. Valid datawheet will be available to the eight data output drivers within tACC Access Time after the last address input signal is stable, providing that CE and OE access times are also satisfied. Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode.

If the CE low transition occurs simultaneously with or later than the WE low transition datashheet Write Cycle 1, the output buffers remain in a high impedance state during this period. All AC and DC electrical characteristics are valid over the full operating temperature range. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in a high-impedance state during this period.

If WE is low or the WE fs1225y transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high impedance state during this period. During power—up, when VCC rises above approximately 3.

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Dsy datasheet pdf

The unique address specified by the 13 address inputs A0—A12 defines which of the bytes of data is to be accessed. WE must return to the high state for a minimum recovery time tWR before another cycle can be initiated. AA designates the year of manufacture. Storage Temperature Lead Temperature soldering, 10s Note: WE is high for a read cycle. All AC and DC electrical characteristics are valid over the full operating temperature range.

WE is high for a read cycle. The expected tDR is defined as starting at the date of manufacture. The latter occurring falling edge of CE or WE will determine the start of the write cycle. If the CE low transition occurs simultaneously with or later than the WE low transition in Write Cycle 1, the output buffers remain in a high-impedance state during this period.

There is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. Why bother to spell words correctly. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.

Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. DM Quad 2-Input Exclusive. All address inputs must be kept valid throughout the write cycle.

All address inputs must be kept valid throughout the write cycle.